Avrora

Architecture:

The interface state:

[source]
The state of the simulation program, including the values ??of general purpose registers, IO registers, data memory, program memory, the program counter, etc.. is exposed through an interface called State.
The methods of the interface state allow customers to inspect the program state, regardless of the implementation actually used by the simulator. It provides tools for profiling and monitoring with a convenient interface to inspect the condition without becoming dependent example of the implementation in detail.

The interpreter:

[source]
The interpreter executes the program instructions. In many ways, the interpreter drives the simulation, because it causes the passage of simulation time. The interpreter is a visitor who maintains a program counter that keeps track of the current instruction in the program.
The interpreter is organized in a simple, one main loop of execution of individual instructions and controls the individual methods implement the functionality of each instruction.

The microcontroller interface:

[source]
In addition to the execution of each individual instructions available in the instruction set AVR, a faithful simulation of devices on the microcontroller is necessary to simulate the behavior of the program. While the class interpreter performs the calculation specified by the program instructions, for modularity does not implement each of the devices. Another abstraction layer encapsulates the interpreter and the on-chip peripherals supplied by a particular microcontroller implementation.
The microcontroller interface abstracts the implementation details such as the size of main memory and stores the program, the clock frequency, and on-chip peripherals.

The interface IOReg:

[source]
The AVR architecture has a set of memory mapped registers that are used to communicate and schedule on-chip provided on the microcontroller. The microcontroller encapsulates an instance of the class and provides Simulator devices such as on-chip timer, the analog to digital converter, devices etc.. to communicate with the simulation through the interface and the interface IOreg event queue.

Application areas

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